Title :
Design of a 20 MHz 64-tap transversal filter
Author :
Stearns, Chip C. ; Luthi, Daniel A. ; Ruetz, Peter A. ; Ang, Peng H.
Author_Institution :
LSI Logic Corp., Palo Alto, CA, USA
Abstract :
The authors describe the architecture and design of a high-speed CMOS VLSI filter processor. The internal architecture of the design is pipelined to achieve a sustained 20-MHz data throughput rate. This translates into an effective computational rate of 1.2 billion multiplications (and a similar number of additions) per second. The chip is reconfigurable for one- and two-dimensional filtering, the total device count is 240000 transistors, and the die size is 1.4 cm×1.4 cm. Tap design, data-flow organization, and clock distribution are discussed
Keywords :
CMOS integrated circuits; VLSI; digital filters; signal processing; 20 MHz; 20 MHz 64-tap transversal filter; CMOS VLSI; clock distribution; data-flow organization; tap design; Arithmetic; Computer architecture; Equations; Filtering; Kernel; Nonlinear filters; Process design; Registers; Throughput; Transversal filters;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25765
