DocumentCode
3443563
Title
Analysis of High Voltage LDMOS Power Consumption
Author
Wu, Xiu-Long ; Chen, Jun-ning ; Ke, Dao-ming
Author_Institution
Anhui Univ., Hefei
fYear
2007
fDate
23-25 May 2007
Firstpage
888
Lastpage
890
Abstract
According to the high voltage LDMOS macromodel established in previous work, the inverter consists of LDMOS with high resistance drift region was analyzed. A formulation was presented to solve the power consumption of LDMOS power integrated circuits. The results are shown in good agreement with the simulation values by the two-dimensional numerical simulator MEDICI. Finally, a method to reduce circuit power consumption was presented.
Keywords
MOS integrated circuits; low-power electronics; power consumption; power integrated circuits; 2D numerical simulator; LDMOS power integrated circuits; circuit power consumption; high resistance drift region; high voltage LDMOS power consumption; Analytical models; Circuit simulation; Computational modeling; Energy consumption; Inverters; Medical simulation; Nonlinear equations; Numerical simulation; Power integrated circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics and Applications, 2007. ICIEA 2007. 2nd IEEE Conference on
Conference_Location
Harbin
Print_ISBN
978-1-4244-0737-8
Electronic_ISBN
978-1-4244-0737-8
Type
conf
DOI
10.1109/ICIEA.2007.4318536
Filename
4318536
Link To Document