A high performance CMOS chipset for FFT processors

The authors describe a chipset (processor and controller) developed recently to implement the FFT (fast Fourier transform) algorithm on silicon. As the result of the highly parallel and concurrent architecture, the FFT processor built with one chip set can operate at a computing rate of about 500 million operations per second and an I/O transfer rate of about 5 billion b/s when running with 50-MHz input clock frequency. Utilizing multiprocessing techniques built into the architecture, the aggregated throughput is linearly proportional to the number of nodes employed in the FFT processor system. Using five nodes, each node consisting of a chip set, it can perform a 1024-point complex FFT in 21 μs