Title :
Scaling the high-performance double-gate SOI MOSFET down to the 32 nm technology node with SiO/sub 2/-based gate stacks
Author :
Barin, Nicola ; Braccioli, Marco ; Fiegna, Claudio ; Sangiorgi, Enrico
Author_Institution :
ENDIF, Ferrara Univ.
Abstract :
We apply state-of-the-art simulation to investigate the possibility to scale the UTB-DG MOSFET using rather conventional SiO2-based dielectrics with a minimum thickness of 1 nm, a lower limit set by the need for process yield and reproducibility. The analysis include short-channel effects, gate leakage tunneling current, ON-current and the intrinsic switching delay-time CV/I
Keywords :
MOSFET; dielectric materials; leakage currents; silicon compounds; silicon-on-insulator; 32 nm; ON-current; SiO2; UTB-DG MOSFET; double-gate SOI MOSFET; gate leakage tunneling current; gate stacks; short-channel effects; switching delay-time; CMOS technology; Dielectric constant; Doping profiles; Gate leakage; High-K gate dielectrics; Leakage current; MOSFET circuits; Reproducibility of results; Threshold voltage; Tunneling;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609423
