The application of compiler-assisted multiple-instruction retry to VLIW architectures

Two compiler-assisted multiple-instruction word retry schemes for very long instruction word (VLIW) architectures are described. The first scheme compacts the compiler-generated hazard-free code with different degrees of rollback capability for scalar processors, and inserts no-ops in the scheduled code words. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards