Title :
Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections
Author :
Watanabe, Naoya ; Kojima, Takeaki ; Asano, Tanemasa
Author_Institution :
Center for Microelectron. Syst., Kyushu Inst. of Technol., Fukuoka
Abstract :
We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 mum/20 mum. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device
Keywords :
integrated circuit interconnections; large scale integration; wafer bonding; 10 micron; 3D LSI; 3D integration systems; bump bonding; chip stacking; high-density area bump interconnections; strain generation; wafer-level compliant bump; Capacitive sensors; Closed loop systems; Fabrication; Gold; Large scale integration; Pressing; Resists; Stacking; Temperature; Wafer bonding;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609440
