A channelized DSSS ultra-wideband receiver

Critical to the design of a digital ultra-wideband (UWB) receiver is the ability for the analog-to-digital converter (ADC) to efficiently sample and digitize the UWB signal of several gigahertz. Designing a single ADC to operate at such frequencies is impractical, and parallel ADC architectures with each ADC operating at a fraction of the effective sampling frequency need to be devised. A parallel receiver architecture that efficiently samples and processes the UWB signal at a fraction of the chip frequency is proposed. The received signal is channelized in the frequency domain by employing a bank of mixers and lowpass filters. After sampling at a much reduced frequency, digital filters then operate directly on the sampled signals in each subband channel to optimally estimate multiple spread codes in parallel