Author_Institution :
Univ. of California, Irvine, Irvine, CA, USA
Abstract :
A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don´t Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has bee- measured to be about 1 part per million, RMS.
Keywords :
CMOS integrated circuits; clocks; comparators (circuits); digital-analogue conversion; jitter; phase locked loops; programmable logic devices; readout electronics; sample and hold circuits; shift registers; CMOS; PLL-based sampling clock; analog readout; circular array; comparator offsets; comparators; continuous sample acquisition; continuous synchronous sampling capability; digitization circuit; don´t care-any state; frequency 2 GHz; fully-differential shift register; high-speed clock generation; jitter; multiGHz synchronous waveform acquisition; on-chip digitization; on-chip programmable logic array; per-comparator digital to analog converters; phase-locked loop; real-time pattern-matching trigger generation; real-time programmable windowed trigger generation; reference level adjustment; sample and hold circuits; sample clock generation; size 0.25 mum; transient waveform capturing; Arrays; Bandwidth; Clocks; Phase locked loops; Real-time systems; Shift registers; Synchronization; Analog to digital conversion; phase-locked loop; sample and hold; transient digitizer; trigger circuit;