Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

Author

Okano, K. ; Izumida, T. ; Kawasaki, H. ; Kaneko, A. ; Yagishita, A. ; Kanemura, T. ; Kondo, M. ; Ito, S. ; Aoki, N. ; Miyano, K. ; Ono, T. ; Yahashi, K. ; Iwade, K. ; Kubota, T. ; Matsushita, T. ; Mizushima, I. ; Inaba, S. ; Ishimaru, K. ; Suguro, K. ; Eg

Author_Institution

SoC Res. & Dev. Center, Toshiba Corp., Yokohama

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

721

Lastpage

724

Abstract

The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate length down to 20 nm. The combination of both process technology enables us to fabricate the smallest FinFET on bulk Si substrate reported to date

Keywords

CMOS integrated circuits; MOSFET; elemental semiconductors; silicon; 10 nm; 20 nm; CMOS FinFET fabrication; Si; bulk silicon substrate; device size scalability; punch through stopper; short channel effect control; CMOS process; CMOS technology; Etching; Fabrication; FinFETs; Oxidation; Scalability; Shape control; Silicon; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609454

Filename

1609454