Selective epitaxial channel ground plane thin SOI CMOS devices

A thin SOI ground plane (GP) design is explored for CMOS application beyond 65nm generation node. The ground plane design is implemented using dopant implants at zero degree angle, in contrast to conventional halo implants, which are typically done at large implant angles. The large angle implants may become impracticable as neighboring devices are positioned closer to each other in an ultra-scaled CMOS technology. An intrinsic Si channel layer is epitaxially grown on top of the ground plane layer for improved surface layer transport. The high doping ground plane layer is positioned away from the top interface, minimizing the counter-doping effect in the extension region, resulting in reduced extension resistance. We demonstrate that the GP structure is effective in achieving superior DIBL and subthreshold slope characteristics down to Leff of ~35nm. We also show that junction penalties in thin body SOI ground plane devices are within the acceptable range. We demonstrate high speed ground plane CMOS ring oscillators, a stage delay of ~4.7ps is achieved at Vdd of 0.9V and 1muA/mum standby leakage current