Title :
Optimized emitter wrap-through cells for monolithic module assembly
Author :
Hacke, Peter ; Gee, James ; Kumar, Prabhat ; Howarth, James ; Gonzales, Victoria ; Pratt, Larry ; Strümpel, Claudia ; Dominguez, Jason ; Franklin, Jeff ; Lopez, Gabe ; Corwine, Caroline ; Dawson, Lon
Author_Institution :
Advent Solar, Inc., Albuquerque, NM, USA
Abstract :
Migration from the previous generation of Advent Solar emitter wrap-through (EWT) cells to the current technology platform based on 243 cm2 multicrystalline Si cells and monolithically interconnected cell and encapsulated modules has brought with it significant performance increases. Extraction of current from multiple contact pads distributed on the cell rear, optimization of the emitter through-holes, and reduction of through-hole lengths associated with moving to thinner silicon wafers has led to significantly reduced series resistance. Ag metallization costs are also lowered because of the reduction of grid finger lengths. Improved isolation between interdigitated p and n regions on the cell rear has lead to negligible shunt resistance losses. This, in combination with understanding of diode recombination losses, passivation, and optimization of Si material for the cell design through appropriate choice of base resistivity has lead to a greater than one percent absolute efficiency improvement over previous generation EWT cells, with best multicrystalline Si cells producing 17% conversion efficiency using the regular production processes. Additional improvements to efficiency are obtained with the implementation of texturing. These efficiency gains are further leveraged on the module level by the reduction of series resistance losses associated with the backplane interconnect design compared to conventionally interconnected front-side contacted cells.
Keywords :
elemental semiconductors; encapsulation; integrated optoelectronics; optical backplanes; passivation; silicon; silver; solar cells; Ag; Ag metallization; Si; advent solar emitter wrap-through cells; backplane interconnect design; base resistivity; cell design; cell rear; contact pads; diode recombination losses; emitter through-holes; encapsulated modules; grid finger lengths; interdigitated regions; monolithic module assembly; monolithically interconnected cell; multicrystalline Si cells; optimized emitter wrap-through cells; passivation; series resistance losses; shunt resistance losses; silicon wafers; through-hole lengths; Assembly; Contact resistance; Costs; Design optimization; Fingers; Light emitting diodes; Metallization; Passivation; Silicon; Solar power generation;
Conference_Titel :
Photovoltaic Specialists Conference (PVSC), 2009 34th IEEE
Conference_Location :
Philadelphia, PA
Print_ISBN :
978-1-4244-2949-3
Electronic_ISBN :
0160-8371
DOI :
10.1109/PVSC.2009.5411433