Title :
[Copyright notice]
Abstract :
The following topics are dealt with: ESD failure, modeling and simulation of on-chip ESD and latch-up effects; on-chip ESD protection for HV CMOS and bipolar; magnetoresistive devices (GMR/TMR); system level ESD; on-chip ESD protection strategies for digital I/O design; modeling and simulation of on-chip ESD and latch-up effects; and TLP/HBM/CDM testing - testers and methodology.
Keywords :
CMOS digital integrated circuits; bipolar digital integrated circuits; electrostatic discharge; failure analysis; giant magnetoresistance; integrated circuit design; integrated circuit modelling; integrated circuit testing; magnetoresistive devices; tunnelling magnetoresistance; CDM testing; ESD failure; HBM testing; HV CMOS; TLP testing; bipolar; digital I/O design; latch-up effect; magnetoresistive devices; on-chip ESD protection;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-5853-7115-0
