Design and Implementation of a DPA Resistant AES Coprocessor

To improve the DPA resistance of cryptographic device in intellectual cards, a power analysis platform is constructed for AES. After analyzed the AES encrypt process, a MASK circuit, disturbance circuit for clock and disturbance circuit for power are designed and implemented in an AES coprocessor of ZTEIC Corporation´s intellectual card. The AES coprocessor can process data with 900 Mbps at 100 MHz frequency. The DPA test result shows the proportion of best DPA results is less than 5%, and with mask information. The AES coprocessor can defend DPA better than other products with a higher throughput.