Ultra-low power consumption military communication systems

The authors present general techniques to reduce the power consumption while increasing the clock rate and maximizing the silicon area of CMOS circuits. Modern digital signal processing implementations suffer from high power dissipation while requiring large silicon area. A technique based on the use of additional transistors with a modified threshold is described. This technique lowers the power-delay product of transmission-gate intensive CMOS circuits compared to standard CMOS technology. Resulting circuits exhibit a reduced power dissipation while enabling increased clock rate and reduced implementation area by a factor of 2. Use of additional circuit optimization techniques improves the efficiency of CMOS circuits by a factor of 3 to 4