MOSAIC V-a very high performance bipolar technology

The authors describe the initial implementation of MOSAIC V (Motorola oxide isolated self-aligned implanted circuits, fifth generation), a novel silicon process technology. A number of innovative process approaches and novel methods of aggressive device scaling result in deep submicron device structures in the range of 0.1-0.4 μm. A very low speed-power product of 92 fJ at 3.3-V supply voltage for ECL (emitter coupled logic) gates is obtained in the lower range of operating currents, with typical gate delays of 73 ps at 100 μA and 35 ps at 800 μA switch currents. Using a selectively implanted collector, a minimum ECL gate delay of 29 ps at 800 μA switch current is achievable