Multi-Gbits/s silicon bipolar multiplexer and demultiplexer with interleaved architectures

Interleaved architectures for time-division multiplexers and demultiplexers with synchronous parallel loading and unloading are proposed. Initial four-bit implementation on a 100-ps ECL (emitter coupled logic) silicon array produces multiplexer operation above 4 Gb/s and demultiplexer above 5 Gb/s. The circuits operate from a single -4.5-V supply and use F100K logic levels for all inputs and outputs. Both architectures can be expanded to 8 or 16 bits without any significant data rate reductions