Analysis and implications of ic cooling for deep nanometer scale cmos technologies

Cooled chip operation is being seriously evaluated as a practical technique for boosting the performance of high-end microprocessors. This paper presents, for the first time, a comprehensive analysis of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies. Unlike all previous work, our analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While cooling always gives performance gain at the device or circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and the associated cost may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots