DocumentCode :
3446443
Title :
New constraint for Vth optimization for sub 32nm node CMOS gates scaling
Author :
Morifuji, Eiji ; Kapur, Pawan ; Chao, Andy Kuo-An ; Nishi, Yoshio
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA
fYear :
2005
fDate :
5-5 Dec. 2005
Lastpage :
1029
Abstract :
We show new constraint of Vth scaling for logic blocks from inverter operation viewpoint. In lower Vth region, delay time in inverter chain saturates because of the loss in overdrive for the input of MOSFETs. This loss dominates the inverter speed in scaled V dd region and we propose a new relaxed scaling scenario. This accounts for the speed loss using a simplified model which adequately manifests the new phenomenon
Keywords :
CMOS integrated circuits; MOSFET; invertors; CMOS gates scaling; MOSFET; delay time; inverter operation; lower threshold voltage region; threshold voltage optimization; threshold voltage scaling; Chaos; Computational Intelligence Society; Constraint optimization; Degradation; Delay; Inverters; MOS devices; MOSFETs; Power dissipation; Ring oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
Type :
conf
DOI :
10.1109/IEDM.2005.1609539
Filename :
1609539
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3446443
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