DocumentCode
3446648
Title
A fully SiO2-isolated self-aligned SOI-bipolar transistor for VLSIs
Author
Nishizawa, H. ; Azuma, S. ; Yoshitake, T. ; Yamada, K. ; Ikeda, T. ; Masuda, H. ; Anzai, A.
Author_Institution
Hitachi Ltd., Tokyo, Japan
fYear
1991
fDate
9-10 Sep 1991
Firstpage
53
Lastpage
58
Abstract
A fully functional high-speed 6K-gate SOI ECL gate array has been realized. An advanced fabrication process was developed to obtain a fully SiO2-isolated self-aligned SOI-bipolar transistor for VLSIs. Novel temperature control techniques were also utilized. The power consumption of the VLSI is 18 W. The temperature gradient of the SOI-BJT (bipolar junction transistor) was studied by means of transistor-array measurements and three-dimensional finite-element-method simulations. The analysis suggests that the temperature rise of the SOI-BJT is about 6°C/mW, which is only 3°C/mW larger than that of an Si-BJT. A fully functional 6K-gate ECL gate array has been fabricated using the SOI-SEPT (selective etching of polysilicon technology) process
Keywords
VLSI; bipolar integrated circuits; bipolar transistors; emitter-coupled logic; integrated circuit technology; logic arrays; semiconductor-insulator boundaries; silicon compounds; 18 W; 3D FEM simulation; ECL gate array; SOI-BJT; SOI-SEPT; SOI-bipolar transistor; Si-SiO2; VLSI; fabrication process; fully SiO2-isolated; polysilicon technology; power consumption; selective etching; self-aligned; temperature control techniques; Dielectrics; Etching; Fabrication; Isolation technology; Parasitic capacitance; Silicon; Temperature control; Transistors; Very large scale integration; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar Circuits and Technology Meeting, 1991., Proceedings of the 1991
Conference_Location
Minneapolis, MN
Print_ISBN
0-7803-0103-X
Type
conf
DOI
10.1109/BIPOL.1991.160955
Filename
160955
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