DocumentCode :
3446733
Title :
A New Model K*TDG and High Level Exploring Algorithm
Author :
Li, Guangshun ; Ma, Guangsheng ; Wu, Junhua
Author_Institution :
Harbin Eng. Univ., Harbin
fYear :
2007
fDate :
23-25 May 2007
Firstpage :
1701
Lastpage :
1705
Abstract :
A new model K*TDG is proposed in this paper to solve the problem of complex data flow decomposing and exploring, where k indicates the compactness of the system parameters. In the following, the attributes of K*TDG and its primary operations are discussed, and a decomposing and exploring algorithm is proposed. In order to decrease the algorithm complexity, a group strategy on the degree of polynomials of complex components is shown. Experimental results indicate that using the algorithm and strategy in this paper, keeping the area and delay approximate optimization, the exploring space is decreased greatly.
Keywords :
circuit complexity; high level synthesis; polynomial approximation; system-on-chip; K*TDG model; algorithm complexity; complex data flow; decomposing algorithm; delay approximate optimization; high level exploring algorithm; polynomials degree; system on chip; system parameters; Arithmetic; Circuit synthesis; Data engineering; Delay; Hardware design languages; Libraries; Polynomials; Space exploration; Space technology; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial Electronics and Applications, 2007. ICIEA 2007. 2nd IEEE Conference on
Conference_Location :
Harbin
Print_ISBN :
978-1-4244-0737-8
Electronic_ISBN :
978-1-4244-0737-8
Type :
conf
DOI :
10.1109/ICIEA.2007.4318700
Filename :
4318700
Link To Document :
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