Junction Engineering of 1T-DRAMs

One-transistor dynamic random access memories (DRAMs) (1T-DRAMs) are considered a promising candidate to overcome the limits of scalability of conventional one-transistor/one-capacitor DRAMs. Robust and reproducible operation has been demonstrated by experiments in MOSFET devices with a gate length (L) down to ~50 nm, which prevents their use in future technological nodes. The main factors limiting the retention time of 1T-DRAMs are the Shockley-Read-Hall recombination in the channel and the band-to-band tunneling between channel and source/drain junctions, both enhanced by the relatively high field at both junctions. In this letter, we show through statistical device simulations on a template double-gate MOSFET that, by introducing an underlap of ~16 nm between the drain (source) junction and the gate, it is possible to reduce both the electric field at the junction and the impact of process variability, achieving 1T-DRAMs with L = 10 nm with a retention time in excess of 100 ms. We also show that field plates at the source and drain contacts do not provide additional advantages and that the junctionless transistor operation as 1T-DRAM is totally undermined by the impact of random dopants.