Title :
Degradation of rise time in NAND gates using 2.0 nm gate dielectrics
Author :
Ogas, M.L. ; Price, P.M. ; Kiepert, J. ; Baker, R.J. ; Bersuker, G. ; Knowlton, W.B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Boise State Univ., ID, USA
Abstract :
CMOS NAND gate circuit performance degradation caused by a single pMOSFET wearout induced by constant voltage stress in 2.0 nm gate dielectrics is examined using a switch matrix technique. The NAND gate rise time is found to increase by approximately 64%, which may lead to timing errors in high frequency digital circuits. The degraded pMOSFET reveals that a decrease in drive current by 41% and an increase in threshold voltage by 18% are directly proportional to an increase in channel resistance, thereby substantially increasing the NAND gate circuit timing delay.
Keywords :
CMOS logic circuits; MOS logic circuits; dielectric materials; logic gates; 2 nm; CMOS NAND gate circuit performance degradation; NAND gates; channel resistance; constant voltage stress; gate dielectrics; high frequency digital circuits; pMOSFET wearout; rise time degradation; switch matrix technique; threshold voltage; timing delay; Circuit optimization; Degradation; Dielectrics; Frequency; MOSFET circuits; Stress; Switches; Switching circuits; Timing; Voltage;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2005 IEEE International
Print_ISBN :
0-7803-8992-1
DOI :
10.1109/IRWS.2005.1609564
