DocumentCode
3447008
Title
Impact of boron penetration at the p+-poly/gate-oxide interface on the device reliability of deep submicron CMOS logic technology
Author
Nayak, Deepak K. ; Ming-Yin Hao ; Rakkhit, Rajat
Author_Institution
Div. of Logic Technol., Adv. Micro Devices Inc., Sunnyvale, CA, USA
fYear
1996
fDate
20-23 Oct 1996
Firstpage
116
Lastpage
118
Abstract
Impact of boron penetration at the p+-poly/gate-oxide interface is investigated. It is shown that the onset of boron penetration at this interface can not be detected by conventional threshold or flatband voltage shifts of p-channel devices, but it results in significantly lower QBD and Vt instability. Constant current stress in inversion has been found to be most sensitive technique to monitor the onset of boron at the p+-poly/gate-oxide interface
Keywords
CMOS logic circuits; boron; chemical interdiffusion; integrated circuit measurement; integrated circuit reliability; ion implantation; rapid thermal annealing; 975 to 1025 C; B penetration; BF2 implant energy; QBD; RTA; Si:B-SiO2:B; constant current stress in inversion; deep submicron CMOS logic technology; device reliability; gate oxide reliability; p-channel devices; p+-poly/gate-oxide interface; threshold voltage instability; Annealing; Boron; CMOS technology; Capacitance; Capacitance-voltage characteristics; Degradation; Design for quality; Implants; Temperature; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop, 1996., IEEE International
Conference_Location
Lake Tahoe, CA
Print_ISBN
0-7803-3598-8
Type
conf
DOI
10.1109/IRWS.1996.583395
Filename
583395
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