Predictive simulation to improve reliability of a snapback-based NMOS clamp

Author

Gaitonde, Prasad G. ; Gaul, Stephen J. ; Crandell, Thomas L. ; Earles, Susan K.

Author_Institution

Florida Inst. of Technol., Melbourne, FL

fYear

2005

fDate

17-20 Oct. 2005

Abstract

To incorporate high current electro-static discharge (ESD) conditions, we have extended a NMOS SPICE model to include models of a parasitic BJT, body (substrate) resistance and impact ionization current. The approach taken models the geometry and layout dependence of the NMOS, making the model scalable. The developed model predicts trigger voltages of MOS and BJT qualitatively and with reasonable accuracy. Clamps having longer body to source spacing are seen to trigger the parasitic BJT faster, irrespective of the MOS channel length. The parasitic BJT device parameters do not have significant effect on the clamp turn-on voltage

Keywords

MOSFET; avalanche breakdown; bipolar transistors; electrostatic discharge; impact ionisation; semiconductor device breakdown; semiconductor device models; semiconductor device reliability; MOS channel length; NMOS SPICE model; avalanche current; body resistance; clamp turn-on voltage; electrostatic discharge; impact ionization current; parasitic BJT models; snapback-based NMOS clamp; trigger voltages; Clamps; Electrostatic discharge; Geometry; Immune system; Impact ionization; MOS devices; Predictive models; SPICE; Solid modeling; Voltage; NMOS; SPICE Model; avalanche current; body resistance; parasitic BJT; trigger voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2005 IEEE International

Conference_Location

S. Lake Tahoe, CA

Print_ISBN

0-7803-8992-1

Type

conf

DOI

10.1109/IRWS.2005.1609578

Filename

1609578