DocumentCode :
3447620
Title :
Toward a practical methodology for completely characterizing the optimal design space
Author :
Blythe, Stephen A. ; Walker, Robert A.
Author_Institution :
Rensselaer Polytech. Inst., Troy, NY, USA
fYear :
1996
fDate :
6-8 Nov 1996
Firstpage :
8
Lastpage :
13
Abstract :
One of the most compelling reasons for developing high-level synthesis systems has been the desire to quickly explore the design space. Since this problem is very difficult to solve optimally, most systems compute either lower bounds or estimates on the optimal tradeoff curve. The methodology described here goes beyond most previous work in several ways: (1) it computes all optimal tradeoff points so as to completely characterize the design space, (2) it solves not only the scheduling problem, but the clock determination and module selection problems as well, and (3) it carefully prunes the search space at each level of the design cycle
Keywords :
high level synthesis; logic CAD; clock determination; design space; high-level synthesis; lower bounds; module selection; optimal design space; optimal tradeoff curve; optimal tradeoff points; scheduling problem; search space; Clocks; Computer science; Delay; Design methodology; High level synthesis; Libraries; Mathematics; Processor scheduling; Space exploration; Time factors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Synthesis, 1996. Proceedings., 9th International Symposium on
Conference_Location :
La Jolla, CA
ISSN :
1080-1820
Print_ISBN :
0-8186-7563-2
Type :
conf
DOI :
10.1109/ISSS.1996.565870
Filename :
565870
Link To Document :
بازگشت