Title :
A low voltage four-quadrant CMOS analogue multiplier
Author :
Lin, Zhi-Ming ; Huang, C.H.
Author_Institution :
Dept. of Ind. Educ., Nat. Changhua Univ. of Educ., Taiwan
Abstract :
A four-quadrant CMOS analogue multiplier is presented. Experimental results show that the multiplier has a dynamic input range, exceeding 60% of the power supply voltage (±0.5 V), and the linearity error is less than 0.07% at the maximum input range. The simulated maximum power dissipation for the multiplier is 2.83 mW
Keywords :
CMOS analogue integrated circuits; analogue multipliers; low-power electronics; -0.5 V; 1.83 mW; 5 V; CMOS analogue multiplier; LV multiplier; dynamic input range; four-quadrant analogue multiplier; low linearity error; low voltage operation; CMOS process; CMOS technology; Circuits; Dynamic range; Electricity supply industry; Linearity; Low voltage; Mirrors; RF signals; Transconductance;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.814415
