A synthesis of switched capacitor frequency dependent negative capacitor using common delay branches

Switched-Capacitor (SC) higher-order immittance simulations have been reported in the literature. However, most of these circuits are SC Frequency Dependent Negative Resistors (FDNR), and the other SC higher-order immittance simulation circuits have been seldom reported. The main reason for this seems to lie in the complexity of the circuits. In this paper SFG representation of SC Frequency Dependent Negative Capacitor (FDNCAP) behavior is shown and delay branches in SC FDNCAP are combined into a common delay branch (CDB) to build a simple circuit structure. SC FDNCAP proposed uses a unity gain buffer (UGB) in common with other SC circuits. The circuit is controlled by a simple two phase control clock. The capacitor value spreads and the sum of the capacitor values is small. The effect of parasitic capacitance is minimized. To confirm basic operations of the circuits proposed, simulation results by SWITCAP are also shown