Title :
Optimization and design of fast transceiver for DSL application in CMOS technology
Author_Institution :
Infineon Technol., Munich, Germany
Abstract :
Circuit optimization and design for a multi-bit rate fast transceiver for application of ISDN to SDSL rates (from 160 kb/s up to 2.3 Mb/s) is proposed. In the transmitter path is a sigma-delta time continuous multi-bit 14-bit DAC. It includes dynamic averaging for linearity improvement with simple filtering. The hybrid is also optimized using passive elements for the loop variations and with additional active filters for additional rejection. It is integrated for the simple reason of eliminating the high SNR requirement from the multi-bit sigma-delta ADC in the receive path (using AGC)
Keywords :
CMOS integrated circuits; ISDN; analogue-digital conversion; circuit optimisation; digital subscriber lines; digital-analogue conversion; high-speed integrated circuits; integrated circuit design; mixed analogue-digital integrated circuits; sigma-delta modulation; transceivers; 14 bit; 160 kbit/s to 2.3 Mbit/s; AGC; ASIC; CMOS technology; DSL application; ISDN rates; SDSL rates; active filters; continuous-time DAC; dynamic averaging; high speed transceiver; linearity improvement; multi-bit DAC; multi-bit rate transceiver; sigma-delta DAC; Active filters; Circuit optimization; DSL; Delta-sigma modulation; Design optimization; Filtering; ISDN; Linearity; Transceivers; Transmitters;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.814425
