Floating-point analog-to-digital converter

Author

Yuan, Jiren ; Piper, Johan

Author_Institution

Dept. of Appl. Electron., Lund Univ., Sweden

Volume

3

fYear

1999

fDate

1999

Firstpage

1385

Abstract

A floating-point ADC (FP-ADC) has been proposed for the purpose of achieving a wide dynamic range without demanding a high resolution, when the high resolution is merely for covering the signal dynamic range rather than the quantization accuracy. In an FP-ADC, the dynamic range and resolution can be designed independently. Unlike the known logarithmic amplifier solution, it directly gives a linear digital output. It can work with a small input range imposed by a low voltage supply as its virtual input range is greatly expanded. The principle, key circuitry, achievable performance and sensitivities to mismatches are addressed in this paper. Simulation results indicate that this approach is capable of achieving up to a 16 bit dynamic range with an 8-10 bit effective resolution at a sampling rate of 40 MS/s in submicron CMOS

Keywords

CMOS integrated circuits; analogue-digital conversion; floating point arithmetic; 0.35 micron; 20 MHz; 8 to 10 bit; analog-to-digital converter; floating-point ADC; linear digital output; low voltage supply; mismatch sensitivity; resolution; submicron CMOS; wide dynamic range; Analog-digital conversion; CMOS technology; Circuit simulation; Circuit synthesis; Dynamic range; Low voltage; Quantization; Sampling methods; Signal design; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.814428

Filename

814428