Fault tolerant communication in 3D integrated systems

3D integration is an emerging technology that promises higher integration densities and performances and low power dissipation. Stacked 3D integrated systems consist in layers of active silicon connected with vertical wires called Thru-Silicon-Vias (TSV). The high defect rates of 3D systems cumulate the intra-die and inter-die interconnect parametric variations. Thus, the susceptibility to permanent and transient faults increases. In this paper fault tolerant communication in 3D systems is achieved by spare via insertion and signal coding. As single error correction (SEC) capabilities are not enough to ensure the targeted level of communication reliability in 3D technologies, multi-error correction capabilities are achieved by block/ interleaved SEC codes. Data bits are split in blocks, individually encoded using SEC codes. Due to current 3D integrated manufacturing processes, achieving a good yield is one of the current challenges of this technology. In this paper, interconnect yield improvement is achieved auto reconfiguration by using spare via insertion.