Title :
SOM on multi-FPGA ISA board-hardware aspects
Author :
Suzuki, D. ; Hammami, O.
Author_Institution :
Aizu Univ., Fukushima, Japan
Abstract :
This paper describes the hardware design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. The SOM designed includes 16 neurons controlled in a SIMD execution mode. The application targeted is 3D to 2D projection. The clock frequency of the hardware design is 11.386 MHz and it has been implemented on 5 Xilinx FPGA chips mounted on a plug-an-play PC ISA board. The resulting hardware outperforms under some conditions several software simulations implementations running on various PC hardware
Keywords :
add-on boards; field programmable gate arrays; logic CAD; logic partitioning; parallel processing; self-organising feature maps; 11.386 MHz; 3D to 2D projection; SIMD execution mode; SOM; Xilinx FPGA chips; artificial neural network; hardware design; multi-FPGA ISA board; plug-an-play PC board; self-organizing map ANN; Artificial neural networks; Clocks; Field programmable gate arrays; Frequency; Instruction sets; Neural network hardware; Neural networks; Neurons; Space technology; Unsupervised learning;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.814431
