Gate input reconfiguration for combating soft errors in combinational circuits

Many techniques to relieve soft error problem, such as making the circuit larger, called upsizing, have been developed under tight limitation in circuit performance but they all call for a tradeoff between performance and soft error resilience. In this paper, we present a soft error reduction technique, called gate input reconfiguration, to combat soft errors in digital circuits without additional overhead. Substantiated by SPICE simulations, our device level experiments disclose that gate inputs and transistor positions in a gate have a profound impact on circuit probability of failure due to soft errors. The detailed study on soft error vulnerabilities of several types of logic gates lead us to develop a gate input reconfiguration technique in order to improve the reliability of large combinational circuits. This overhead-free technique rearranges gate input pins such that soft error rate of that gate is minimized. Experimental results reveal that the proposed technique provides considerable decrease in the probability of failure due to soft errors of benchmark circuits. We observed this decrease to be as much as 45% in some circuits. Next, we combine the use of gate input reconfiguration technique with upsizing technique to reduce the failure due to soft errors even further. The combination of these two techniques achieves very impressive reliability improvements.