DocumentCode
3448025
Title
Design of Low-Power Double Edge-Triggered Flip-Flop Circuit
Author
Chien-Cheng, Yu
Author_Institution
Hsiuping Inst. of Technol, Ta-Li
fYear
2007
fDate
23-25 May 2007
Firstpage
2054
Lastpage
2057
Abstract
In this paper, we proposed a double edge-triggered (DET) flip-flop suitable for low-power applications. In addition, the proposed flip-flop can be implemented with fewer transistors than any previous circuit. Simulations have verified the correct operation of the proposed DET flip-flop, for a variety of clock and data rates. Simulation results indicated that the proposed circuit is capable of significant delay and power saving.
Keywords
flip-flops; logic design; low-power electronics; clock rates; data rates; double edge-triggered flip-flop circuit; low-power design; CMOS technology; Circuit simulation; Clocks; Delay; Energy consumption; Flip-flops; Latches; Master-slave; Switches; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics and Applications, 2007. ICIEA 2007. 2nd IEEE Conference on
Conference_Location
Harbin
Print_ISBN
978-1-4244-0737-8
Electronic_ISBN
978-1-4244-0737-8
Type
conf
DOI
10.1109/ICIEA.2007.4318771
Filename
4318771
Link To Document