DocumentCode :
3448208
Title :
Pipelined virtual camera configuration for real-time image processing based on FPGA
Author :
Jin, Seung Hun ; Cho, Jung Uk ; Jeon, Jae Wook
Author_Institution :
Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon
fYear :
2007
fDate :
15-18 Dec. 2007
Firstpage :
183
Lastpage :
188
Abstract :
Real-time image processing is important for many application areas which require a quick response from events in a scene. Since real-time image processing involves large amount of computations, many approaches have been proposed to solve this problem especially using a dedicated hardware system. However, they are not sufficiently adapted to practical use because their dedicated hardware architecture is not suitable to carry out multiple tasks even in the case of a reconfigurable architecture. This paper proposes a pipelined virtual camera configuration which can perform several image processing tasks, especially at the low and intermediate levels, through the reconfiguration of the system. By synchronizing the entire system with the pixel clock, each processing modules can regard the others as a virtual camera. As a result, both the performance and the degree of reconfiguration are significantly increased.
Keywords :
field programmable gate arrays; image processing; reconfigurable architectures; FPGA; dedicated hardware architecture; pipelined virtual camera configuration; pixel clock; real-time image processing; reconfigurable architecture; Cameras; Clocks; Computer architecture; Field programmable gate arrays; Hardware; Image processing; Layout; Real time systems; Reconfigurable architectures; Synchronization; FPGA; Image Processing; Virtual Camera;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Robotics and Biomimetics, 2007. ROBIO 2007. IEEE International Conference on
Conference_Location :
Sanya
Print_ISBN :
978-1-4244-1761-2
Electronic_ISBN :
978-1-4244-1758-2
Type :
conf
DOI :
10.1109/ROBIO.2007.4522157
Filename :
4522157
Link To Document :
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