High-throughput, low complexity, parametrizable VLSI architecture for full search block matching algorithm for advanced multimedia applications

In this paper a new VLSI architecture, called ALPHA-B, for the motion estimation full-search algorithm is proposed. It features high throughput/area efficiency and high block size flexibility for a small hardware complexity. This circuit concurrently processes different block sizes, N/2×N/2 and N×N, permitting for the Advanced Prediction (AP) option of the H.263/MPEG-4 standards. It is fully parametrizable in terms of block (N) and search area (p) sizes thus allowing for QCIF/CIF/4CIF image format processing. This architecture was implemented on a 0.25 μm CMOS technology in order to realize two IP macro-cells to be integrated in single-chip H.263/MPEG coders. The cases of 30 frames/s CIF and 4CIF formats with a search area of -16/+15 were considered. The resulting CIF-format ASIC features a core area of 1.5 mm² for a clock frequency of 72 MHz while the 4CIF-format ASIC is characterized by a core area of 3.84 mm² for a clock frequency of 105 MHz