A Pipelined Interpolating Analog-to-Digital Converter with Reduced Nonlinearity Error

An interpolating analog-to-digital converter (ADC) using pipelined architecture is designed. In order to obtain a high linearity of the ADC, a differential difference amplifier (DDA) with well restrained nonlinearity error is adopted to reduce the nonlinearity error. Furthermore, a latched comparator is proposed to achieve a low kickback noise, which is of great importance to the linearity of the ADC. The ADC is implemented in a 0.35 mum standard digital CMOS process with a single 3.3 V supply, and achieves 8 bit resolution at speeds up to 50 MSamples/s.