Title :
A low voltage high resolution pipelined incremental ADC
Author :
Azzopardi, G. ; Grech, I. ; Micallef, J. ; Maloberti, F.
Author_Institution :
Dept. of Microelectron., Malta Univ., Msida, Malta
Abstract :
A low voltage incremental analog-to-digital converter with a pipelined architecture is presented. Using first order modulators the conversion time is significantly reduced even at low sampling rates while maintaining high resolution. The switched capacitor converter is designed to operate with a 1.8 V power supply and uses three pipelined modulators. With careful design and digital correction it is possible to achieve more than 15 bit resolution
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; low-power electronics; pipeline processing; switched capacitor networks; 0.8 micron; 1.8 V; 15 bit; LV CMOS ADC; SC convertor; analog-to-digital converter; conversion time reduction; digital correction; first order modulators; high resolution ADC; low voltage operation; pipelined incremental ADC; pipelined modulators; switched capacitor converter; Analog-digital conversion; Capacitors; Clocks; Low voltage; Microelectronics; Pipelines; Sampling methods; Sensor phenomena and characterization; Signal resolution; Switching converters;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.814454
