Title :
Double-regenerated switched-current comparator
Author :
Worapishet, Apisak ; Hughes, John B. ; Toumazou, Chris
Author_Institution :
Mahanakorn Univ. of Technol., Bangkok, Thailand
Abstract :
A double-regeneration (DR) technique in switched-current comparators is described in this paper. The technique uses the comparator´s memory transistors not only as a calibration stage but also as a regenerative amplifier. This provides an enhanced speed with no penalty on noise and minimum added complexity and power. Practical simulation indicates a multiplexed DR comparator operating at a promising bandwidth of 270 MHz which is an improvement in speed by a factor of ~1.35 over the multiplexed basic comparator
Keywords :
CMOS analogue integrated circuits; comparators (circuits); multiplexing; switched current circuits; 270 MHz; calibration stage; double-regenerated SI comparator; multiplexed comparator; regenerative amplifier; switched-current comparator; Bandwidth; Calibration; Educational institutions; Flip-flops; Laboratories; Niobium; Parasitic capacitance; Switching circuits; Transconductance; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.814462
