An analytical current, delay, and power model for the submicron CMOS inverter

We present an analytical model for computing the supply current, delay, and power in a submicron CMOS inverter using a modified version of the `n-th power law´ MOSFET model. By first computing definable reference points on the output voltage waveform and then using linear approximations through these points to find the actual points of interest, the desired speed and accuracy of the inverter model are achieved. The most important part of the analysis is a three-step process for computing the time and output voltage when the `short-circuit´ transistor changes its mode of operation. The model has been validated using an accurate, physically based, submicron MOSFET model for a wide range of inverter sizes, input transition times, and capacitive loads: it can predict the delay, peak supply current, and power dissipation to within a few percent of simulation results, while offering about two orders of magnitude gain in CPU time