Title :
A multiprocessor architecture for high-rate communication processing
Author :
Johnson, Eric C.
Author_Institution :
New Mexico State Univ., Las Cruces, NM, USA
Abstract :
The author presents a general-purpose multiprocessor architecture which accommodates an I/O bandwidth of many Gb/s through the use of VRAM in the main memory. The virtual port memory architecture is a global-memory-message-passing multiprocessor which is well suited to I/O-intensive real-time processing. This bus-based architecture permits incremental adjustments in I/O bandwidth, memory size, and processing power by simply adding or removing I/O controllers, memory modules, and processors. This architecture is described, followed by an analysis of its performance in handling various communication processing tasks, including the 4×300 Mb/s data stream at the NASA Tracking and Data Relay Satellite System (TDRSS) ground terminal
Keywords :
computer networks; data communication systems; multiprocessing systems; parallel architectures; satellite relay systems; telecommunications computing; NASA Tracking and Data Relay Satellite System; VRAM; bus-based architecture; data communication; global-memory-message-passing multiprocessor; high-rate communication processing; multiprocessor architecture; performance; virtual port memory architecture; Application software; Communication switching; Computer aided instruction; Computer architecture; Hardware; Memory architecture; Military computing; Packet switching; Performance analysis; Switches;
Conference_Titel :
Military Communications Conference, 1991. MILCOM '91, Conference Record, Military Communications in a Changing World., IEEE
Conference_Location :
McLean, VA
Print_ISBN :
0-87942-691-8
DOI :
10.1109/MILCOM.1991.258421
