A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing

Author

Strollo, Antonio G M ; Napoli, Ettore ; Cimino, C.

Author_Institution

Dept. of Electron. & Telecommun., Naples Univ., Italy

Volume

3

fYear

1999

fDate

1999

Firstpage

1631

Abstract

A novel architecture for real time Synthetic Aperture Radar (SAR) signal processing is presented. Presently, notwithstanding the use of expensive parallel computers and FET techniques, available SAR processors are unable to achieve real time performance. The proposed architecture achieves real time processing by using a recently proposed signum coded algorithm and time domain processing implemented in a custom VLSI architecture based on systolic arrays

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; correlators; digital signal processing chips; image coding; pipeline processing; radar computing; radar imaging; real-time systems; synthetic aperture radar; systolic arrays; time-domain analysis; CMOS ASIC; SAR processor; VLSI processor; custom VLSI architecture; light-weight SAR imaging; radar signal processing; real-time SAR imaging; signum coded algorithm; signum coded signal processing; synthetic aperture radar; systolic arrays; time domain processing; Central Processing Unit; Circuits; Computer architecture; Convolution; Data processing; Radar polarimetry; Signal processing; Signal processing algorithms; Synthetic aperture radar; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.814486

Filename

814486