A new architecture for bandpass sigma delta analogue to digital conversion

A new architecture for the implementation of bandpass sigma-delta A/D converters is described. The proposed architecture is hardware-efficient end has improved performance over existing topologies. A chopping scheme is used to shift signals from the passband to DC and a lowpass modulator used to perform the conversion. In the new implementation, the passband location is limited only by the maximum capacitor sampling rate possible, while in previous converters it was limited by the much slower integrator clock rate. Hence, the new converter can digitize bands at much higher frequencies than previous implementations. Simulation results are presented for a second-order modulator running at 1.07 MHz converting an input band at 10.7 MHz, a typical radio intermediate frequency