A global optimization tool for CMOS logic circuits

Transistor sizing has been proved to be a very efficient technique for improving the performance of CMOS logic circuits in terms of both speed and power consumption. In this paper, new simple and accurate delay and power models are proposed: these models are integrated with time efficient algorithms for the transistor size optimization of large, generic CMOS circuits. Additionally the developed tool includes models for the noise evaluation: as one of the effects of noise in high performance circuits is the increasing of the delay along critical paths, the adopted noise model has been integrated in the delay equations, with the aim of improving the quality of the performed optimization