• DocumentCode
    3449160
  • Title

    A reconfigurable hardware unit for the HMAC algorithm

  • Author

    Khan, Esam ; El-Kharashi, M. Watheq ; Gebali, Fayez ; Abd-El-Barr, Mostafa

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Victoria Univ., BC
  • fYear
    2005
  • fDate
    5-6 Dec. 2005
  • Firstpage
    861
  • Lastpage
    874
  • Abstract
    HMAC is a shared-key security algorithm that uses hash functions for message authentication and data integrity. The most popular hash functions used with HMAC are MD5, SHA-1, and RIPEMD-160, which are all based on the function MD4. IPSec uses HMAC with these three hash functions for message authentication. In addition, these hash functions can be used with other security applications, such as digital signature. In a previous work, we designed a unified engine that implements the three hash algorithms. In this work, we integrated the HMAC algorithm into that engine to form a reconfigurable HMAC-hash unit, which implements six standard security algorithms and can be reconfigured at runtime to perform any one of them. We applied the pipelining principle to the design of the HMAC-hash unit. Hence, the larger the message size, the better the throughput. Compared to other work, we achieve better throughput than those integrating three or more hash functions and a comparable throughput to those integrating two hash functions. We achieve comparable results to those integrating HMAC with some hash functions. The area utilization of the designed unit is less than 33% of the available logic on the FPGA chip we used. Thus, the designed unit can fit on a single FPGA chip as an SoC
  • Keywords
    cryptography; data integrity; digital signatures; field programmable gate arrays; logic design; FPGA chip; HMAC algorithm; IPSec; MD5; RIPEMD-160; SHA-1; data integrity; digital signature; hash functions; message authentication; reconfigurable hardware unit; shared-key security algorithm; Algorithm design and analysis; Data security; Digital signatures; Engines; Field programmable gate arrays; Hardware; Message authentication; Pipeline processing; Runtime; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information and Communications Technology, 2005. Enabling Technologies for the New Knowledge Society: ITI 3rd International Conference on
  • Conference_Location
    Cairo
  • Print_ISBN
    0-7803-9270-1
  • Type

    conf

  • DOI
    10.1109/ITICT.2005.1609672
  • Filename
    1609672