A high-speed CMOS track/hold circuit

Author

Zin, Mohd Asmawi Mohamed ; Kobayashi, Haruo ; Kobayashi, Kazuya ; Ichimura, Jun-Ichi ; San, Hao ; Onaya, Yoshitaka ; Kimura, Yasuyuki ; Yuminaka, Yasushi ; Sasaki, Yoshisato ; Tanaka, Kouji ; Abe, Fuminori

Author_Institution

Dept. of Electron. Eng., Gunma Univ., Japan

Volume

3

fYear

1999

fDate

1999

Firstpage

1709

Abstract

This paper describes the design of a high-speed CMOS track/hold circuit in front of an ADC. The track/hold circuit employs differential open-loop architecture, very linear source follower input buffers, NMOS sampling switches and bootstrap sampling-switch driver circuits for high-speed operation with 3.3 V supply voltage. SPICE simulations with MOSIS 0.35 μm CMOS BSIM 3v3 parameters showed that it achieves the signal-to-(noise+distortion)-ratio (SNDR) of more than 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mW power consumption. A test circuit was fabricated with MOSIS 0.8 μm CMOS process and its measured results show that the proposed circuit topology performs a track/hold operation

Keywords

CMOS analogue integrated circuits; SPICE; bootstrap circuits; circuit simulation; driver circuits; high-speed integrated circuits; sample and hold circuits; 0.35 micron; 0.8 micron; 100 MHz; 3.3 V; 40 mW; NMOS sampling switches; SPICE simulations; bootstrap sampling-switch driver circuits; circuit topology; differential open-loop architecture; high-speed CMOS; linear source follower input buffers; power consumption; signal-to-(noise+distortion)-ratio; track/hold circuit; Circuit simulation; Circuit testing; Driver circuits; Energy consumption; MOS devices; SPICE; Sampling methods; Switches; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.814505

Filename

814505