Title :
Cell optimization for 500 V n-channel IGBTs
Author :
Parthasarathy, V. ; So, K.C. ; Shen, Z. ; Chow, T.P.
Author_Institution :
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
fDate :
31 May-3 Jun 1994
Abstract :
The impact of cell design on the safe operating area (SOA) of n-channel IGBTs is assessed. It is shown that the atomic layer lattice (ALL) cell geometry is important for improving the latchup dominated SOA of 500 V n-channel IGBTs. Experimental results for the latchup performance of n-channel ALL cell IGBTs, presented for the first time, show that even at a temperature of 200°C these devices do not latch at all but are instead current limited. The experimental measurements and tradeoffs for the different cell geometries have been found to corroborate the trends in the numerical simulations
Keywords :
insulated gate bipolar transistors; 200 C; 500 V; SOA; atomic layer lattice cell geometry; cell optimization; current limiting; latchup performance; n-channel IGBTs; safe operating area; Atomic layer deposition; Avalanche breakdown; Breakdown voltage; Geometry; Implants; Insulated gate bipolar transistors; Ionization; Lattices; Semiconductor optical amplifiers; Temperature;
Conference_Titel :
Power Semiconductor Devices and ICs, 1994. ISPSD '94., Proceedings of the 6th International Symposium on
Conference_Location :
Davos
Print_ISBN :
0-7803-1494-8
DOI :
10.1109/ISPSD.1994.583652
