DocumentCode :
3449779
Title :
A coarse-grain phased logic CPU
Author :
Reese, Robert B. ; Thornton, Mitchell A. ; Traver, Cherrice
Author_Institution :
Mississippi State Univ., MS, USA
fYear :
2003
fDate :
12-15 May 2003
Firstpage :
2
Lastpage :
13
Abstract :
A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed implementation scheme known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of PL blocks. Each PL block is composed of control logic wrapped around a collection of DFFs and LUT4s to form a multi-input/output PL gate. PL offers a speedup technique known as early evaluation that can be used to boost performance at the cost of additional logic within each block. In addition to early evaluation, this implementation uses bypass paths in the ALU for shift and logical instructions and buffering stages for increased dataflow to further improve performance. Additional speedup is gained by reordering instructions to provide more opportunity for early evaluation. Simulation results show an average speedup of 41% compared to the clocked netlist over a suite of five benchmark programs.
Keywords :
flip-flops; microprocessor chips; pipeline processing; table lookup; 4-input Lookup Tables; D-Flip-Flops; MIPs ISA; buffering stages; bypass paths; coarse-grain phased logic CPU; control logic; five-stage pipelined CPU; multiinput/output PL gate; reordering; self-timed implementation scheme; speedup technique; Automatic control; Clocks; Costs; Design methodology; Educational institutions; Engineering management; Instruction sets; Logic design; Physics computing; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium on
ISSN :
1522-8681
Print_ISBN :
0-7695-1898-2
Type :
conf
DOI :
10.1109/ASYNC.2003.1199161
Filename :
1199161
Link To Document :
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