10 Gbps implementation of TLS/SSL accelerator on FPGA

This paper proposes the one-chip architecture to mount all processes for TLS/SSL ciphered communication into one FPGA or ASIC, and shows the 10 Gbps implementation of low-power (23 W) TLS/SSL accelerator on 65 nm FPGA. The usage of FPGA/ASIC enables high efficient processing and low-power consumption by using parallel, optimized and pipelined processing. One-chip architecture achieves high throughput by using a switch to avoid the congestion in exchanging data between multiple processing-blocks. In this research, to reduce the circuit area in the one-chip architecture, high-efficient processing design (a parallel processing circuit shared with multiple data, and a circuit shared in transmitting and receiving) was used. In addition, to enhance the operating frequency, a switch downsized by sharing a port to exchange data with multiple blocks decreased the number of wires. By means of these designs, circuit area to implement all TLS/SSL processes was reduced to less than that of 65 nm FPGA used in this research, and 166 MHz operating frequency required to realize 10 Gbps throughput at 64-bit pipeline was achieved. In experimental evaluation using prototype, 23 W power consumption and 10 Gbps encryption throughput were achieved.