Author_Institution :
VLSI Syst. Res. Center, Technion-Israel Inst. of Technol., Haifa, Israel
Abstract :
Transferring data between mutually asynchronous clock domains requires safe synchronization. However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get "optimized" to the point where they do no longer operate correctly. This paper reviews a number of such cases, analyzes the causes of the errors, and offers a correct synchronizer circuit for each case. A correct two flop synchronizer is presented. After discussing cases that avoid synchronization, the following synchronizers are reviewed: one flop, sneaky path, greedy path, wrong protocol, global reset, async clear, DFT leakage, pulse, slow-to-fast, metastability blocker, parallel and shared flop synchronizers.
Keywords :
asynchronous circuits; clocks; design for testability; synchronisation; system-on-chip; DFT leakage; global reset; greedy path; metastability blocker; mutually asynchronous clock domains; shared flop synchronizers; sneaky path; synchronization; two flop synchronizer; wrong protocol; Circuits; Clocks; Delay; Error correction; Frequency synchronization; Latches; Metastasis; Protocols; Radio access networks; Very large scale integration;