Title :
Delay-insensitive, point-to-point interconnect using m-of-n codes
Author :
Bainbridge, W.J. ; Toms, W.B. ; Edwards, D.A. ; Furber, S.B.
Author_Institution :
Dept. of Comput. Sci., Univ. of Manchester, UK
Abstract :
m-of-n codes can be used for carrying data over selftimed on-chip interconnect links. Such codes can be chosen to have low redundancy, but the costs of encoding/decoding data is high. The key to enabling the cost-effective use of m-of-n codes is to find a suitable mapping of the binary data to the code. This paper presents a new method for selecting suitable mappings through the decomposition of the complex m-of-n code into an incomplete m-of-n code constructed from groups of smaller, simpler m-of-n and 1-of-n codes. The circuits used both for completion detection and for encoding/decoding such incomplete codes show reduced logic size and delay compared to their full m-of-n counterparts. The improvements mean that the incomplete m-of-n codes become attractive for use in on-chip interconnects and network-on-chip designs.
Keywords :
CMOS logic circuits; asynchronous circuits; codes; decoding; delays; encoding; integrated circuit interconnections; logic design; binary data mapping; completion detection; delay reduction; delay-insensitive interconnect; encoding/decoding; m-of-n codes; network-on-chip designs; point-to-point interconnect; selftimed on-chip interconnect links; Costs; Decoding; Delay; Encoding; Integrated circuit interconnections; Latches; Logic circuits; Logic design; Network-on-a-chip; Wires;
Conference_Titel :
Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium on
Print_ISBN :
0-7695-1898-2
DOI :
10.1109/ASYNC.2003.1199173